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Winbond W83626F
LPC-to-ISA Bridge
W83626F/W83626D
W83626F/W83626D Data Sheet Revision History
Version Pages 1 2 3 4 5 6 7 8 9 1 0 n.a. Dates 02/25/00 Version 0.50 on Web 0.50 Main Contents First published.
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date:Feb. 2000 Preliminary Revision 0.50
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LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
GENERAL DESCRIPTION
W83626F/W83626D is a transparent LPC-to-ISA bus conversion IC. For the new generation Intel chipset Camino and Whitney, SiS Super South 960, featuring LPC bus, there is no support for ISA bus and slots. However the demand of ISA devices still exist. For such case, W83626F is the best companion solution for the non-ISA chipset. Also the packages of W83626F had been chosen to be the most economic solution for save the M/B board layout size and cost. For the new generation chipset featuring LPC interface and support no ISA bus, W83627HF (Winbond LPC I/O) together with the set of W83626F is the complete solution.
FEATURES
LPC to ISA Bridge
* * * * * * * * * * * * * *
Meet LPC Spec. 1.1 Support LDRQ# (LPC DMA), SERIRQ (serial IRQ)
Full ISA Bus Support except ISA Bus Masters 5V ISA and 3.3V LPC interfaces
All Software Transparent
IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ Supports 3 fully ISA Compatible Slots without Buffering
LPC Bus at 33MHz
Supports Programmable ISA Bus Divide the PCI Clock into 3 or 4 All ISA Signals can be Isolate
14.318MHz in to generate two 14.318MHz buffer out and one 24.576MHz Specific Keyboard Functions supported Support 8 programmable general purpose I/O pins
Supports Configuration registers for programming performance
PACKAGE
* 128-pin PQFP for W83626F
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Block diagram OF W83626F
LFRAM# PCIRST# LAD[3:0] PCICLK LDRQ# SERIRQ LPC Interface ISA Interface
ISOLATE#
Signal Isolation Control
SA[19:0] SD[15:0] BALE AEN IOCHRDY IOCS16# IOCHK# IOR# IOW# LA[23:17] SBHE# MEMCS16# MEMR# MEMW# SMEMR# SMEMW# ZEROWS# MASTER# REFRESH# ROMCS# RSTDRV SYSCLK IRQ[3:7,9:12,14,15] DRQ[0:3,5:7] DACK[0:3,5:7]
3.3V 5V
Power SuppIy
14.318M
CLOCK GEN. / BUF.
14MOUT1 14MOUT2 24.576M
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
PIN CONFIGURATION FOR 626F
LA23 LA22 VCC5 LA21 LA20 LA19 LA18 GND LA17 MEMR# MEMW# SD8 SD9 SD10 SD11 SD12 SD13 VCC5 SD14 SD15 MASTER#/RTCEN DRQ7 GND DACK7# DRQ6 DACK6#/HEFRAS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
SBHE# BALE TC DACK2# IRQ3 IRQ4 IRQ5 GND IRQ6 IRQ7 SYSCLK REFRESH# DRQ1 DACK1# DRQ3 DACK3# IOR# VCC5 IOW# SMEMR# SMEMW# OWS# GND DRQ2 IRQ9 RSTDRV IOCHCK# SD7 SD6 SD5 SD4 SD3 VCC5 SD2 SD1 SD0 GPIO7/IOHCS# GPIO6/RTCCS# 11 1 99 9 9 999 99 9 88 888888 8 877 7 7 77 77 7 7 66 66 6 0 0 0 9 8 7 6 5 4 3 21 0 9 8 7 6 5 432 1 098 7 6 5 4 3 2 1 0 9 8 7 6 5 21 0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
W83626F LPC to ISA
GPIO5/IRQ8 GPIO4/PLED GPIO3/IRQIN IOCHRDY GND AEN SA19 SA18 SA17 VCC5 SA16 SA15 SA14 SA13 GND SA12 SA11 SA10 SA9 VCC5 SA8 SA7 SA6 SA5 GPIO2/MCCS# GPIO1/KBCS#
1 1 1 1 1 1 1 1 1 12 2 2 2 22 2 2 2 2 3 3 3 3 3 3 33 3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 90 1 2 3 45 6 7 8 9 0 1 2 3 4 5 67 8
DRQ5 DACK5# DRQ0 DACK0# VCC5 IRQ14 IRQ15 IRQ12 IRQ11 IRQ10 IOCS16# MEMCS16# LFRAM# PCIRST# GND LAD3 LAD2 LAD1 LAD0 VCC3 PCICLK LDRQ# SERIRQ PWRDN# AVCC3 14.318M 14MOUT1 14MOUT2 24.576M AGND SA0 SA1 SA2 SA3 SA4 80PCS#/KBEN# ROMCS# GPIO0/IRQ1
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
1. PIN DESCRIPTION
I/O12t I/O24t I/O12tp3 I/O24tp3 I/OD12t I/O24t OUT12 OUT24 O12p3 O24p3 OD12 OD24 INcs INt INtd INtu INts INtsp3 - TTL level bi-directional pin with 12 m A source-sink capability - TTL level bi-directional pin with 24 m A source-sink capability - 3.3V TTL level bi-directional pin with 12 m A source-sink capability - 3.3V TTL level bi-directional pin with 24 m A source-sink capability - TTL level bi-directional pin open drain output with 12 m A sink capability - TTL level bi-directional pin with 24 m A source-sink capability - TTL level output pin with 12 m A source-sink capability - TTL level output pin with 24 m A source-sink capability - 3.3V TTL level output pin with 12 m A source-sink capability - 3.3V TTL level output pin with 24 m A source-sink capability - Open-drain output pin with 12 m A sink capability - Open-drain output pin with 24 m A sink capability - CMOS level Schmitt-trigger input pin - TTL level input pin - TTL level input pin with internal pull down resistor - TTL level input pin with internal pull up resistor - TTL level Schmitt-trigger input pin - 3.3V TTL level Schmitt-trigger input pin
W83626F PIN DESCRIPTION
LPC Interface SYMBOL LAD[3:0] LFRAME# PCICLK PCIRST# SERIRQ LDRQ# PIN 16-19 13 21 14 23 22 I/O I/O12tp3 INtsp3 INt INtsp3 I/OD12t O12tp3 FUNCTION These signal lines communicate address, control and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. PCICLK provides timing for all transactions on the LPC bus. All LPC signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge. Reset signal. It can connect to PCIRST# signal on the host. Serial IRQ Input/Output. Encoded DMA Request signal.
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
LPC Interface, continued SYMBOL PWRDN# PIN 24 I/O INtu FUNCTION Power Down. The signal is active low according to CR 44 Bit 7and wake-up enable by hardware setting. There are eight different power-down states (Power down Mode 3).
ISA Interface Signals SYMBOL SA[19:17] PIN 58-56 I/O OUT24 FUNCTION System Address Bus. These are the upper address lines that define the ISA's byte granular address space (up to 1 M byte). SA[19:17] are at an unknown state upon PCIRST#. System Address Bus. These are the bi-directional lower address lines that define the ISA's byte granular address space (up to 1 M byte). SA[16:0] are at an unknown state upon PCIRST#.
SA[16:0]
54-51 49-46 44-41 35-31
OUT24
SD[15:0]
122-1 21 119-1 14 75-71 69-67
OUT24
System Data. SD[15:0] provide the 16-bit data path for devices residing on the ISA Bus. The W83626F tri-states SD[15:0] during PCIRST#.
AEN
59
OUT24
Address Enable. AEN is asserted during DMA cycles. This signal is also driven high during W83626F initiated refresh cycles. AEN is driven low upon PCIRST#. I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive data on to the ISA data bus (SD[15:0]). I/O Write. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus (SD[15:0]). I/O Channel Ready. Resources on the ISA Bus negate IOCHRDY to indicate that additional time (wait states) is required to complete the cycle. ISA System Clock. SYSCLK is the reference clock for the ISA bus. The SYSCLK is generated by dividing PCICLK by 3 or 4. Reset Drive. W83628F asserts RSTDRV to reset devices that reside on the ISA Bus. The W83628F asserts this signal while the PCIRST# is asserted. 16-bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles.
IOR# IOW#
86 84
OUT24 OUT24
IOCHRDY SYSCLK
61 92
INt OUT24
RSTDRV IOCS16#
77 11
OUT24 INt
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
ISA Interface Signals , continued SYMBOL PIN I/O FUNCTION Memory Chip Select 16. MEMCS16# asserted indicates that the MEMCS16# 12 INt memory slave supports 16-bit accesses. IOCHCK# 76 INt I/O Channel Check. IOCHK# can be driven by any resource on the ISA bus during on detection of an error. Zero Wait States. An ISA slave asserts ZEROWS# after its OWS# 81 INt address and command signals have been decoded to indicate that the current cycle can be executed as an ISA zero wait state cycle. ZEROWS# has no effect during 16-bit I/O cycles. 103-1 OUT24 Unlatched Address. The LA[23:17] address lines are LA[23:17] bi-directional. These address lines allow accesses to physical 04 memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs 106-1 when the W83628F owns the ISA Bus. 09 111 SMEMW# 82 OUT24 Standard Memory Write. SMEMW# asserted indicates the current ISA bus cycle is a memory write cycle to an address below 1 Mbyte. SMEMR# 83 OUT24 Standard Memory Read. SMEMR# asserted indicates the current ISA bus cycle is a memory read cycle to an address below 1 Mbyte. REFRESH# 91 OUT24 Refresh. REFRESH# asserted indicates that a refresh cycle is in progress, or that an ISA master is requesting W83626F to generate a refresh cycle. Upon PCIRST#, this signal is tri-stated. BALE 101 OUT24 Bus Address Latch Enable. BALE is an active high signal asserted by the W83626F to indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE. BALE remains asserted throughout DMA and ISA master cycles. BALE is driven low upon PCIRST#. SBHE# 102 OUT24 System Byte High Enable. SBHE# asserted indicates that a byte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is at an unknown state upon PCIRST#. Memory Read. MEMR# asserted indicates the current ISA bus cycle is a memory read. Memory Write. MEMW# asserted indicates the current ISA bus cycle is a memory write. MASTER#. This signal is used with a DREQ line by an ISA master to gain control of the ISA Bus. RTC Function Enable.The pin applies a pull-down resistor (4.7K ohm) to enable RTC functions ( RTCCS#,and IRQ8) 98 INt Parallel Interrupt Requested Input 3.
MEMR# MEMW# MASTER#
112 113 123
OUT24 OUT24 INt
RTCEN# IRQ3
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
ISA Interface Signals , continued SYMBOL PIN I/O IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DRQ0 97 96 94 93 78 10 9 8 6 7 3 INt INt INt INt INt INt INt INt INt INt INt
FUNCTION
Parallel Interrupt Requested Input 4. Parallel Interrupt Requested Input 5. Parallel Interrupt Requested Input 6. Parallel Interrupt Requested Input 7. Parallel Interrupt Requested Input 9. Parallel Interrupt Requested Input 10. Parallel Interrupt Requested Input 11. Parallel Interrupt Requested Input 12. Parallel Interrupt Requested Input 14. Parallel Interrupt Requested Input 15. DMA Request 0. The DREQ signal indicates that either a slave DMA device is requesting DMA services, or an ISA bus master is requesting use of the ISA bus. DMA Request 1. DMA Request 2. DMA Request 3. DMA Request 5. DMA Request 6. DMA Request 7. DMA Acknowledge 0. The DACK# signal indicates that either a DMA channel or an ISA bus master has been granted the ISA bus. DMA Acknowledge 1. DMA Acknowledge 2. DMA Acknowledge 3. DMA Acknowledge 5. DMA Acknowledge 6. During power-on reset,this is pulled-hi internally(Select 4Eh) and is defined as HEFRAS which provides the power-on value for CR3 bit4 .A 4.7k ohm is recommended if intends to pull down .(Select 2Eh)
DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# HERFRA
90 79 88 1 127 124 4 89 99 87 2 127
INt INt INt INt INt INt OUT24 OUT24 OUT24 OUT24 OUT24 I/OD24t
DACK7# TC
126 100
OUT24 OUT24
DMA Acknowledge 7. Terminal Count. The W83628F asserts TC to DMA slaves as a terminal count indicator.
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
K/B , GPIO AND 80h PCS# Function SYMBOL PIN I/O FUNCTION 80PCS# 36 I/OD12t 80h PORT Chip Select.(Default) KBEN# K/B Functions Enable. During power-on reset this pin is weak pulled-up internally. The pin applied a pull-down resistor (4.7K ohm) to enable K/B functions. (IRQ1,KBCS#,and MCCS#) ROMCS#, this pin enable positive decoder of BIOS address range [depend on CR03 ,bit 1 or external weak pulled-up during PCIRST is asserted] . General purpose I/O pin 0. Parallel Interrupt Requested Input 1. This interrupt request is used for specific K/B functions. General purpose I/O pin 1. Decode the address 60h and 64h to output chip selected signal. Enable by KBEN# power-on setting. General purpose I/O pin 2. Decode the address 62h and 66h to output chip selected signal Enable by KBEN# power-on setting General purpose I/O pin 3. Programmable parallel IRQ input transfers to serial IRQ Enable by KBEN# power-on setting General purpose I/O pin 4. Power LED output, this signal is low after system reset. General purpose I/O pin 5. Parallel Interrupt Requested Input 8. This interrupt request is used for specific RTC functions. Enable by RTCEN# power-on setting General purpose I/O pin 6. Decode the address 70h and 71h to output chip selected signal Enable by RTCEN# power-on setting General purpose I/O pin 7. Decode SA[15-11] are all 0 and setting by CR04 Bit 6.
ROMCS#
37
I/OD12t
GPIO0
38
I/OD12t
IRQ1 GPIO1 KBCS# GPIO2 MCCS# GPIO3 IRQIN GPIO4 PLED GPIO5
39
I/O12t
40
I/OD12t
62
I/OD12t
63
I/OD12t
64
I/OD12t
IRQ8 GPIO6 RTCCS# GPIO7 IOHCS#
65
I/OD12t
66
I/OD12t
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Clock Buffer and Generator SYMBOL PIN I/O 14.318M 26 INt 14MOUT 1 27 OUT12t 14MOUT 2 28 OUT12t 24.576M 29 OUT12t 25.000M FUNCTION Main 14.318 MHz Clock Input. 14.318 MHz Buffer Output 1. 14.318 MHz Buffer Output 2. This pin is weak pull-up during 3 V DD ramp-up period. The default setting is 24.576 MHz and selected 25.000 MHz by external pull-down with 4.7K ohm (recommended) during power ramp-up period. 24.576 MHz Clock Output for Audio Codec or selected 25.000 MHz Clock Output for LAN on board solution.
Power Signals SYMBOL VCC5 VCC3 GND AVCC3 AGND
PIN 5, 45, 55, 70, 85, 105, 120, 20 15, 50, 60, 80, 95, 110, 125 25 30
I/O PWR PWR PWR PWR PWR
FUNCTION Digital 5V Supply. Digital 3.3V Supply. Digital Ground. Analog 3.3V Supply. Analog Ground.
Power-on strapping Signals SYMBOL PIN 80PCS#/KBEN# 36
I/O I/OD12t
ROMCS#
37
I/OD12t
MASTER/RTCEN#
123
INt
DACK6#/HEFRAS
128
I/OD24t
FUNCTION Power-on strapping with pulled-down register will enable K/B and mouse functions. When it is set, pin 38 , 39 and 40 will do IRQ1, KBCS# and MCCS# signals. If there is a boot-ROM (BIOS) ,the signal must power-on with a weak pulled-high register. Power-on strapping with pulled-down register will enable RTC functions. When it is set, pin 64 and 65 will do IRQ8 and RTCCS# signals. Set this function will change the port that is used to access configuration-registers . Default setting is 4Eh ,but by power-on strapping with a pulled-down register change to 2Eh.
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
CONFIGURATION REGISTER
1 Chip (Global) Control Register
Enable the following configuration registers by writing 26h to the location 4Eh twice. Change the location to 2Eh by setting bit4 of CR03 or power-on strapping with a pulled-down register on pin 128 .
CR03 (ROM Decoder Register, Default , 100011s0b)
Bit 7-5 Bit4
Reserved. Configure Address and Value
= 0 Write 26h to the location 4E twice. (4Eh and 4Fh are index and data port) = 1 Write 26h to the location 2E twice(By DACK6 power-on setting with weak pull-down resistor).(The pair are 2Eh and 2Fh)
Bit 3-2
BIOS Decode Range of High Memory.
= 00 1MB BIOS ROM positive decode. = 01 2MB BIOS ROM positive decode. = 10 4MB BIOS ROM positive decode. = 11 8MB BIOS ROM positive decode. (Default setting)
Bit 1
BIOS ROM decoder Enable.
= 0 Disable BIOS ROM decoder. (Default setting) =1 Enable BIOS ROM decoder.
Bit 0
BIOS Protected Mode.
=0 BIOS Writed Disable. (Default setting) =1 BIOS Writed Enable. This bit set to " 1 " for updated BIOS used allow Memory R/W to the range of BIOS decoded. This bit is always set to " 0 " after reset.
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
CR04 (GPIO Status Register , Default 0ss00sssb)
If the GPIO is selected GPIO function, it will be controlled by CR10,13,14,15,and 16.The pins were set non-GPIO functions by power-on setting pin or software programmed. Bit 7(GPIO7) : = 1 Signal used as IOHCS# (Set by software only) = 0 Signal used as GPIO function (Default) Bit 6 (GPIO6): = 1 Signal used as RTCCS# (Set by pin123 RTCEN# ) = 0 Signal used as GPIO function (Default) Bit 5 (GPIO5): = 1 Signal used as IRQ8 (Set by Pin 123 RTCEN# ) = 0 Signal used as GPIO function (Default) Bit 4 (GPIO4): = 1 Signal used as PLED ( Set by software only and programmed by CR CR17 bit [5,4]) = 0 Signal used as GPIO function . (Default) Bit 3 (GPIO3): = 1 Signal used as IRQIN (depended on CR17 bit[3..0]) = 0 Signal used as GPIO function (Default)
Bit 2 (GPIO2): = 1 Signal used as MCCS# (decode address 62h and 66h ) by Pin 36 KBEN# power-on setting = 0 Signal used as GPIO function (Default) Bit 1 (GPIO1): = 1 Signal used as KBCS# (decode address 60h and 64h) by Pin 36 KBEN# power-on setting = 0 Signal used as GPIO (Default) Bit 0 (GPIO0): = 1 Signal used as IRQ1 by Pin 36 KBEN# power-on setting = 0 Signal used as GPIO (Default)
CR05 (System Clock Register , Default 0x4D)
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Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Bit 7
SYSCLK Divider.
= 0 SYSCLK is equal to PCICLK divided by 4. = 1 SYSCLK is equal to PCICLK divided by 3.
Bit 6
8-bit I/O Recovery Enable
= 0 Disable bit [5:3] setting and uses 3.5 SYSCLKs for 8 bit I/O recovery time. = 1 Enable bit [5:3] setting.
Bit 5:3
8-bit I/O Recovery Times .
When bit 6= 1 , these 3 bits field define the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 8 bit I/O = 000 0 SYSCLK = 001 1 SYSCLK = 010 2 SYSCLKs = 011 3 SYSCLKs = 100 4 SYSCLKs = 101 = 110 = 111 5 SYSCLKs 6 SYSCLKs 7 SYSCLKs
Bit 2
= 0 Ignore bits [1:0] setting and uses 3.5 SYSCLKs for 16-bit I/O recovery time. = 1 The 16-bit I/O recovery time is decided by bits 1:0.
Bit 1:0
16-bit I/O Recovery Times.
When bit 2 = 1 , this 2-bit field defines the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 16 bit I/O = 01 1 SYSCLK = 10 2 SYSCLKs = 11 3 SYSCLKs = 00 4 SYSCLKs
CR10 (GPIO0-GPIO7 Function Enable Register, Default 0x00)
Bit 7 - 1: Reserved.
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LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Bit 0:
GPIO Function Activity.
= 1 All GPIO functions are activated . All registers (CR 11,12,13,14,15,16) about GPIO function will be set default value . = 0 All GPIO functions are inactive except the signals by power-on setting. If any one of CR04 bit [7..0] was set non-GPIO function,the bit just affect which was set GPIO function .
CR11, CR12 (Reserved Register For GPIO Control Without Configure Mode Entry ) The register is programmable when the bit 0 of CR10 is set to " 1 " and affected by the settings of CR14 ( I/O Selectioin ) and CR16 ( Inversion ).
User defines port address to control GPIO functions. To control GPIO state without entry configure mode. SA [0..7] can be defined on the bit [0..7] of CR11 and SA [8..15] on the bit [ 0..7] of CR12. For example: Define address 50h in CR11 and 01h in CR12 after reset. bit 0= -GPIO0 (=0 low state, =1 Hi state ) bit 1=-GPIO1 (=0 low state =1 Hi state) ,bit 2=GPIO2,.........,bit 7=GPIO7 the same definition as bit 0. Set CR14 to " 00h " (output port) and CR16 to " 00h " (incoming/outgoing) -o 150 aa ------(10101010) b indicated GP7,GP5,GP3 and GP1 are Hi state. -o 150 55 ------(01010101) b indicated GP6,GP4,GP2,and GP0 are Hi state. - i 150 ------show all states of GPIO[7..0]
CR13 (GPIO0-GPIO7 Address Decoder Rester, Default 0x00 ) The register is programmable when the bit 0 of CR10 is set to " 1 ".
Bit 7:
Address Decoder 2
=1 Enable address decoder .Generate a CS# signal to GPIO port which decided by bit[6..4] ,the specify address in CR34 and CR35 and mask range in CR 33.
=0 Disable address decoder.
Publication Release Date: Feb 2000 Revision 0.50
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LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Bit 6 -Bit 4 :
Address Decoder 2 Output Selection.
Define which GP port as address decoder depended on CR33,CR34 and CR35. = 000 Selected GPIO 0 as CS# = 001 Selected GPIO 1 as CS# = 010 Selected GPIO 2 as CS# = 011 Selected GPIO 3 as CS# = 100 Selected GPIO 4 as CS# = 101 Selected GPIO 5 as CS# = 110 Selected GPIO 6 as CS# = 111 Selected GPIO 7 as CS# output output output output output output output output
Bit 3:
Address Decoder 1
=1 Enable address decoder . Generate a CS# signal to GPIO port which decided by bit[6..4] ,the specify address in CR31 and CR32 and mask range in CR 30.
=0 Disable address decoder.
Bit 2 -Bit 0 :
Address Decoder 1 Output Selection.
Define which GP port as address decoder depend on CR30,CR31 and CR32. = 000 Selected GPIO 0 = 001 Selected GPIO 1 = 010 Selected GPIO 2 = 011 Selected GPIO 3 = 100 Selected GPIO 4 = 101 Selected GPIO 5 = 110 Selected GPIO 6 = 111 Selected GPIO 7 as CS# as CS# as CS# as CS# as CS# as CS# as CS# as CS# output output output output output output output output
CR14 (GPI0-GPIO7 I/O Selection Register, Default 0xFF) The register is programmable when the bit 0 of CR10 is set to " 1 ".
Bit [7..0] are corresponding with GPIO [7..0] . When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
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LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
CR15 (GPIO0-GPIO7 Data Register, Default 0x00) The register is programmable when the bit 0 of CR10 is set to " 1 ".
Bit [7..0] are corresponding with GPIO [7..0] . If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read.
CR16 (GPIO0-GPIO7 Inversion Register, Default 0x00) The register is programmable when the bit 0 of CR10 is set to " 1 ".
Bit [7..0] are corresponding with GPIO [7..0] . When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
CR17 (Power LED & IRQIN Control Register, Default 0x00)
Bit 7 -6:Reserved Bit 5 -4: =00 Power LED pin is tri-stated. =01 Power LED pin is driven low. =10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle. =11 Power LED pin is a 1/4 Hz toggle pulse with 50 duty cycle. Bit 3 - 0: These bits select IRQ resource for IRQIN. Four bits transfer the decimal value to octal system. For example: Bit [3..0] = 1001b = 0x9h means IRQ 9 be selected. Bit [3..0] = 1100b = 0xCh means IRQ12 be selected
CR20 ( Chip ID Register 1, Default 0x62)
Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x 62(read only).
CR21 (Chip ID Register 2 , Default 0x6x)
Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x61(read only). Publication Release Date: Feb 2000 Revision 0.50
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LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Bit [3..0] indicate the version of the chip.
CR30 (Mask Range of Address Decoder 1 Register, Default 0x00)
This register is used to mask address bits (A7~A0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the specify address decoder. For example: If the decoding range is 0x3F8 ~ 0x3FF,you can set 0x3F8 to CR 31, 32 and 07h to CR30 .
CR31, 32 (Address Decoder 1 Specification Register , Default 0x00)
This register contains the address for specify decoder. CR 31 Bit [7..0] are used to define low byte of specity address. CR 32 Bit [7..0] are used to define high byte of specify address. For example: Decoding address was set to be 0x3F5h and write F5h to CR 31 and 03h to CR 32 .
CR33 ((Mask Range of Address Decoder 2 Register, Default 0x00)
This register is used to mask address bits(A7~A0) for specify address decoder , if the corresponding bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the specify address decoder . For example: If the decoding range is 0x3F8 ~ 0x3FF,you can set 0x3F8 to CR 34, 35 and 07h to CR33 .
CR34, 35 Address Decoder 2 Specification Register , Default 0x00)
This register contains the address for specify decoder. CR 34 Bit [7..0] are used to define low byte of specity address. CR 35 Bit [7..0] are used to define high byte of specify address. For example: Decoding address was set to be 0x3F5h and write F5h to CR34 and 03h to CR35. This register contains the address for specify decoder.
- 16 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
CR40 (Clock controllable Register , Default 0x00)
This register is used to enable clock power-down state of the chip. It will shut down 14.318MHz. Bit 7 -1: Reserved. Bit 0 : =1 Power down mode.When entry power down mode , clock output will be turn off. =0 Normal used.
CR41 (Clock tested Register , :Reserved for Winbond internal test) CR42 (Tristate controllable Register(Power-down Mode1) , Default 0x1B)
Bit 7 : REFRESH Cycles Tristated. Bit 6 : SYSCLK Output Tristated. Bit 5 : Address Signals Tristated Enable. Bit 4 - 0 : Defined tristated address signals range.(See Table 1) For example: Define address Bit[4..0] = 0x10h SA [19..16] and LA [23..17] signals will be tristated. Table 1 Set value(Hex) 00 01 02 Tri_state range SA[19..0] and LA[23..17] SA[19..1] and LA[23..17] SA[19..2] and LA[23..17] Workable None one SA[0] SA[1..0]
. .
14 Set value(Hex)
. .
LA[23..17] Tri_state range
. .
SA[19..0] Workable
.
.
.
- 17 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY .
1A 1B
.
LA[23] None one
.
SA[19..0] and LA[22..17] SA[19..0] and LA[23..17]
CR43 (Tristate controllable Register(Power-down Mode2) ,Default 0x07)
The Fast mode is used to improve the performance of transferable interface, because some applications will do fast transaction . To set the suitable bits to decide on specify range or all ISA cycles will meet the requested I/O cycles. Bit 7 : Reserved. Bit 6 : = 1 Enable Fast mode by ADDRESS DECODER 2 and SYSCLK is depended on the state of Bit 3 . = 0 ADDRESS DECORDER 2 doesn't affect Fast Mode and do original operation. Bit 5 : = 1 Enable Fast mode by ADDRESS DECODER 1 and SYSCLK is depended on the state of Bit 3. = 0 ADDRESS DECORDER 1 doesn't affect Fast Mode and do original operatio Bit 4 : = 1 Enable Fast Mode of whole chip, whole ISA cycle of this bridge will be done Fast Mode operation and SYSCLK is depended on the state of Bit 3. = 0 Normal operation, just Bit 6 and Bit 5 can affect Fast Mode operation. Bit 3 : = 1 SYSCLK is equal to PCICLK divided by 1 when decoding range is in Fast Mode. = 0 SYSCLK is equal to PCICLK divided by 2 when decoding range is in Fast Mode. Bit 2 : = 1 Disabled Memory cycles. = 0 Normal used. Bit 1 : = 1 Forced 16 bit cycles . = 0 Normal used. Bit 0 : = 1 8-bit data bus decode only. Only SD [7..0] signals are active. Publication Release Date: Feb 2000 Revision 0.50
- 18 -
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
= 0 Normal used.
CR44 (Tristate controllable Register(Power-down Mode3) , Default 0x07)
Bit 7 : =1 Enable Power-down functions.(ISOLATE# was power-on setting.) =0 Normal used. Bit 6 : Reserved. Bit 5 : =1 SA10 is set as mask (ignored) bit in ADDRESS DECODER 2. The function is used to improved the performance of ECP mode of LPT. If the decoding range is 0x378-0x37F and 0x778-0x77F ,you can set this bit to 1 for Fast Mode operation. = 0 Normal operation. Bit 4 : =1 SA10 is set as mask (ignored) bit in ADDRESS DECODER 1. The function is used to improved the performance of ECP mode of LPT. If the decoding range is 0x378-0x37F and 0x778-0x77F ,you can set this bit to 1 for Fast Mode operation. = 0 Normal operation. Bit 3 : SERIRQ POWER DOWN SELECT. =1 When the chip is in power down mode, the SERIRQ block is inactive. =0 When the chip is in power down mode, the SERIRQ block is active. Bit 2 -0 : Set SYSCLK divided ratio.(2,4,8,16,32,64) = 000 Disable Power-down Mode3. = 001 SYSCLK divided by 2. = 010 SYSCLK divided by 4. = 010 SYSCLK divided by 4 = 011 SYSCLK divided by 8 = 100 SYSCLK divided by 16 = 101 SYSCLK divided by 32 = 110 SYSCLK divided by 64 = 111 LPC I/F,all clocks and signals will be tristated.
- 19 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
CR45 (Wake-Up Event Register, Default 0x01)
Bit 7 :=0 Normal used. =1 Wake up from power-down mode by IRQ 7 occurred. Bit 6 : =0 Normal used. =1 Wake up from power-down mode by IRQ 6 occurred. Bit 5 : =0 Normal used. =1 Wake up from power-down mode by IRQ 5 occurred. Bit 4 : =0 Normal used. =1 Wake up from power-down mode by IRQ 4 occurred . Bit 3 : =0 Normal used. =1 Wake up from power-down mode by IRQ 3 occurred. Bit 2 :Reserved. Bit 1 : =0 Normal used. =1 Wake up from power-down mode by IRQ 1 occurred. Bit 0 : =0 Normal used. =1 Wake up from power-down mode by rising edge of ISOLATE# signal occurred.
CR46(Wake-Up Event Register, Default 0x00)
Bit 7 -5:Reserved Bit 4 : =0 Normal used. =1 Wake up from power-down mode by IRQ 12 occurred . Bit 3 : =0 Normal used. =1 Wake up from power-down mode by IRQ 11 occurred.
- 20 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Bit 2 : =0 Normal used. =1 Wake up from power-down mode by IRQ 10 occurred. Bit 1 : =0 Normal used. =1 Wake up from power-down mode by IRQ 9 occurred. Bit 0 : =0 Normal used. =1 Wake up from power-down mode by IRQ 8 occurred.
CR48 (DMA CYCLES FAST MODE SELECT, Default 0x00)
(Write only)
The Fast mode is used to improve the performance of transferable interface, because some applications will do fast transaction . To set the suitable bits to decide on specify range or all ISA cycles will meet the requested DMA cycles. Bit 7 : = 0 Normal used. = 1 The DMA cycles of channel 7 is in fast mode. Bit 6 : = 0 Normal used. = 1 The DMA cycles of channel 6 is in fast mode. Bit 5 : = 0 Normal used. = 1 The DMA cycles of channel 5 is in fast mode. Bit 4 : Reserved. Bit 3 : = 0 Normal used. = 1 The DMA cycles of channel 3 is in fast mode. Bit 2 : = 0 Normal used. = 1 The DMA cycles of channel 2 is in fast mode. Bit 1 : = 0 Normal used. = 1 The DMA cycles of channel 1 is in fast mode.
- 21 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Bit 0 : = 0 Normal used. = 1 The DMA cycles of channel 0 is in fast mode.
- 22 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
REVISION NOTICES. a. 4/16/1999 modified page 2, 3 to correct wrong typewrite and changed to Rev 0.02. b. 5/18/1999 modified page 1,3 to define K/B functions , 80portCS# and IRQINX.Changed ROMCS#from pin 39 to pin37.page 8,added and modified the function description and changed to Rev0.03 c.5/27/1999 modified page 7 to add power-on setting function in DACK6# for entry port of configure mode(HERFRA). In page 6,Master# was added RTCEN power-on setting function. In page 8,80PCS# was added KBEN power-on setting function and GPIO 5 added a new function IRQ8,GPIO6 added RTCCS#,and GPIO7 added IOHCS#.Rev 0.04 changed. d.5/31/1999 Added Power-Down functin in islate#( page 5)and PLED function in GPIO3(page 8) IRQIN2 was removed and IRQIN1 modified to IRQIN. e.6/8/1999 Renamed ISOLATE# to PWRDN# and corrected RTCCS# decode address (71,72--> 70,71), f. 6/9/1999 modified the function descriptioin of pin 29.Rev 0.05 changed. g.7/9/1999 Combined configuration register and modified new schematic.Rev 0.06. h.7/21/1999 Modified default value of CR and add ed some descriptions and corresponding table. Rev 0.07. i. 8/24/1999 Modified recommended circuit and register descriptions. Corrected power-on setting description of signal ROMCS# . Rev 0.10. j.10/08/1999 modified pin configuration ,pin62 and 63.Rev 0.11 k. 11/16/1999 Modified schematic circuit and added the function description of CR43 and CR44. Rev 0.12. l. 02/20/2000 Add new pacake 100-LQFP (W83626D) dimention
- 23 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Package DIMENSIONS 1 for W83626F (128-pin PQFP)
HE E
102 65
Symbol Min
Dimension in mm
Dimension in inch
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547 0.783
Nom
0.014 0.107 0.008 0.006 0.551 0.787 0.020
Max
0.018 0.113 0.012 0.008 0.555 0.791
103
64
D
HD
128
39
1
e
38
b
A1 A2 b c D E e HD HE L L1 y 0
c
0.25 2.57 0.10 0.10 13.90 19.90
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669 0.905 0.025
0.677 0.913 0.031 0.063
0.685 0.921 0.037
0.08 0 7 0
0.003 7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2 See Detail F Seating Plane A1 y
L L1 Detail F
5. PCB layout please use the "mm".
- 24 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Package DIMENSIONS 2 for W83626D (128-pin LQFP)
HE E
102 65
Symbol Min
Dimension in mm
Dimension in inch
Nom
----1.40 0.16 ----14.00 20.00 0.40 BSC 16.00 ----22.00 0.60 1.00
Max
0.15 1.45 0.23 0.20 14.10 20.10 ------------0.75
Min
0.002 0.053 0.005 0.004 0.547 0.783 ------------0.018
Nom
---0.055 0.006 ----0.551 0.787 0.016 0.630 0.866 0.024 0.039
Max
0.006 0.057 0.009 0.008 0.555 0.791 ------------0.030
103
64
D
HD
128
39
1
e
38
b
A1 A2 b c D E e HD HE L L1 y 0
c
0.05 1.35 0.13 0.10 13.90 19.90 ------------0.45
0.08 0 7 0
0.003 7
Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2 A1 y
See Detail F Seating Plane
L L1 Detail F
5. PCB layout please use the "mm".
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their original owners
- 25 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Recommended circuit for Desktop
IOW# VCC5 IOR# DACK3# DRQ3 DACK1# DRQ1 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# TC OWS# DRQ2 IRQ9 RSTDRV IOCHCK# SD[7..0]
102 SBHE# 101 BALE 100 TC 99 DACK2# 98 IRQ3 97 IRQ4 96 IRQ5 95 GND 94 IRQ6 93 IRQ7 92 SYSCLK 91 REFRESH# 90 DRQ1 89 DACK1# 88 DRQ3 87 DACK3# 86 IOR# 85 VCC5 84 IOW# 83 SMEMR# 82 SMEMW# 81 OWS# 80 GND 79 DRQ2 78 IRQ9 77 RSTDRV 76 IOCHCK# 75 SD7 74 SD6 73 SD5 72 SD4 71 SD3 70 VCC5 69 SD2 68 SD1 67 SD0 66 GPIO7/IOHCS# 65 GPIO6/RTCCS#
IOHCS#
U1
VCC5 C5 0.1UF
C4 0.1UF
NOTE9 : For RTC functions power-on setting used .
MEMR# MEMW#
R3 1K MASTER# DRQ7 DACK7# DRQ6 DACK6#
80PCS#/KBEN#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GPIO0/IRQ1
MEMCS16#
14MOUT1
14MOUT2
PWRDN#
ROMCS#
PCIRST#
IOCS16#
LFRAM#
14.318M
24.576M
DACK5#
DACK0#
SERIRQ
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
PCICLK
LA23 LA22 VCC5 LA21 LA20 LA19 LA18 GND LA17 MEMR# MEMW# SD8 SD9 SD10 SD11 SD12 SD13 VCC5 SD14 SD15 MASTER#/RTCEN# DRQ7 GND DACK7# DRQ6 DACK6#/HEFRAS
W83626F
GPIO5/IRQ8 GPIO4/PLED GPIO3/IRQIN IOCHRDY GND AEN SA19 SA18 SA17 VCC5 SA16 SA15 SA14 SA13 GND SA12 SA11 SA10 SA9 VCC5 SA8 SA7 SA6 SA5 GPIO2/MCCS# GPIO1/KBCS#
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
IOCHRDY
SA[19..0]
AEN
NOTE1: If do not use the GPIO function p please pull-down with a resistor.
LDRQ#
AVCC3
IRQ14
IRQ15
IRQ12
IRQ11
IRQ10
AGND
DRQ5
DRQ0
VCC5
VCC3
LAD3
LAD2
LAD1
LAD0
GND
SA0
SA1
SA2
SA3
SA4
MCCS# KBCS# IRQ1 ROMCS# R1 4.7K
1
2
3
4
5
6
7
8
DRQ5 DACK0# DRQ0 DACK0# IRQ14 IRQ15 IRQ12 IRQ11 IRQ10 IOCS16# MEMCS16# LFRAM# PCIRST#
9
24.576M OSC 14.318M PWRDN# SERIRQ LDRQ# PCICLK
FOR AC97 CODEC
LAD[3..0] LAD[3..0] AVCC3 VCC3 VCC5 C3 0.1UF C1 0.1UF C6 10UF/16V
C2 0.1UF
NOTE2: If do not use the clock output function ,please connect to GND.(Pin 27,28&29)
Title Size B Date: Document Number 626_1.SCH Tuesday, November 16, 1999
W83626F FOR LPC TO ISA BRID
- 15 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
VCC5 VCC5 RP2 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 2 3 4 5 6 7 8 9 10 8.2K VCC5 RP3 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 2 3 4 5 6 7 8 9 10 8.2K VCC5 RP4 SA1 SA0 LA23 LA22 LA21 LA20 LA19 LA18 LA17 2 3 4 5 6 7 8 9 10 8.2K VCC5 R3 IOCHCK# R4 OWS# R5 IOCHRDY R6 MASTER# R13 REFRESH# R11 IOR# R10 MEMR# R1 MEMCS16# R2 IOCS16# R9 SMEMR# R8 SMEMW# IOW# MEMW# R7 R12 8.2K 1K LAD0 LAD1 LAD2 LAD3 LDRQ# SERIRQ LFRAM# 1K 2 3 4 5 6 7 8 8.2K RP7 1K VCC3 PCICLK SERIRQ LFRAM# LDRQ# LAD0 LAD1 LAD2 LAD3 PCIRST# LPC CON1 1 2 3 4 5 6 7 8 9 10 CON20B 11 12 13 14 15 16 17 18 19 20 5VSB +12V VCC3 SMDAT SMCLK -12V -5V +3.3V CB6 0.1uF 1K MASTER# 8.2K 8.2K 1K 1K 1K 1K DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 4.7K 2 3 4 5 6 7 8 8.2K RP8 NOTE4: For ROMCS# power-on seeting used IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DRQ0 DACK5# DRQ5 DACK6# DRQ6 DACK7# DRQ7 1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 2 3 4 5 6 7 8 9 10 8.2K RP1 1 1 SD9 SD10 SD11 SD12 SD13 SD14 SD15 IRQ14 IRQ15 2 3 4 5 6 7 8 9 10 8.2K VCC5 MEMW# MEMR# ROMCS# 31 24 22 WE# OE# CE# GND RP6 1 1 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 2 3 4 5 6 7 8 9 10 8.2K VCC5 RP5 1 VCC5 SA[18..0] For 8M BIOS ROM decode VCC5 U2 J1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 RSTDRV IRQ9 DRQ2 OWS# SD[7..0] SMEMW# SMEMR# IOW# IOR# DACK3# DRQ3 DACK1# DRQ1 SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# TC BALE OSC -5V -12V +12V 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 GND RESDRV +5V IRQ9 -5V DRQ2 -12V 0WS +12V GND SMEMW# SMEMR# IOW# IOR# DACK3# DRQ3 DACK1# DRQ1 REF# CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# T/C BALE +5 OSC GND A/B CHANNEL VCC5 R14 CB5 0.1uF IOCHCK# SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IORDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOCHCK# SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 32
1 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12
VCC
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
W29C040P-90 (PLCC)
16
4.7K J2 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MECS16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DRQ0 DACK5# DRQ5 DACK6# DRQ6 DACK7# DRQ7 +5V MASTER# GND C/D CHANNEL SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR# MEMW# SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SBHE# LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR# MEMW# SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
1
Flash ROM Decoder
1
8.2K
VCC5
PULL HIGH or PULL DOWN RESISTOR
LPC I/F
ISA SLOT
VCC5 VCC3 CB7 0.1uF CB1 0.1uF CB2 0.1uF
VCC3
VCC5
VCC3
CB3 0.1uF
CB4 0.1uF
C7 10uF/16V
C8 10uF/16V
C9 10uF/16V
C10 10uF/16V
inbond
Title W83626 FOR LPC TO ISA BRIDGE Size B Date: Document Number 626_2.SCH Tuesday, August 17, 1999
R15 PWRDN# 1K
WINBOND ELECTRONICS CORP.
Resvered for wake-up
Rev 0.3 Sheet 2 of 2
- 16 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
Recommended circuit for Notebook
- 17 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
IOW# VCC5 IOR# DACK3# DRQ3 DACK1# DRQ1 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# TC OWS# DRQ2 IRQ9 RSTDRV IOCHCK# SD[7..0] SD[7..0]
102 SBHE# 101 BALE 100 TC 99 DACK2# 98 IRQ3 97 IRQ4 96 IRQ5 95 GND 94 IRQ6 93 IRQ7 92 SYSCLK 91 REFRESH# 90 DRQ1 89 DACK1# 88 DRQ3 87 DACK3# 86 IOR# 85 VCC5 84 IOW# 83 SMEMR# 82 SMEMW# 81 OWS# 80 GND 79 DRQ2 78 IRQ9 77 RSTDRV 76 IOCHCK# 75 SD7 74 SD6 73 SD5 72 SD4 71 SD3 70 VCC5 69 SD2 68 SD1 67 SD0 66 GPIO7/IOHCS# 65 GPIO6/RTCCS#
IOHCS#
U1
VCC5 C5 0.1UF
C4 0.1UF
MEMR# MEMW# NOTE9 : For RTC functions power-on setting used .
R3 1K MASTER# DRQ7 DACK7# DRQ6 DACK6#
80PCS#/KBEN#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GPIO0/IRQ1
MEMCS16#
14MOUT1
14MOUT2
PWRDN#
ROMCS#
PCIRST#
IOCS16#
LFRAM#
14.318M
24.576M
DACK5#
DACK0#
SERIRQ
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
PCICLK
LA23 LA22 VCC5 LA21 LA20 LA19 LA18 GND LA17 MEMR# MEMW# SD8 SD9 SD10 SD11 SD12 SD13 VCC5 SD14 SD15 MASTER#/RTCEN# DRQ7 GND DACK7# DRQ6 DACK6#/HEFRAS
W83626F
GPIO5/IRQ8 GPIO4/PLED GPIO3/IRQIN IOCHRDY GND AEN SA19 SA18 SA17 VCC5 SA16 SA15 SA14 SA13 GND SA12 SA11 SA10 SA9 VCC5 SA8 SA7 SA6 SA5 GPIO2/MCCS# GPIO1/KBCS#
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
IOCHRDY
SA[19..0] SA[19..0]
AEN
NOTE1: If do not use the GPIO function pin please pull-down with a resistor.
LDRQ#
AVCC3
IRQ14
IRQ15
IRQ12
IRQ11
IRQ10
AGND
DRQ5
DRQ0
VCC5
VCC3
LAD3
LAD2
LAD1
LAD0
GND
SA0
SA1
SA2
SA3
SA4
MCCS# KBCS# IRQ1 ROMCS# R1 4.7K
1
2
3
4
5
6
7
8
DRQ5 DACK0# DRQ0 DACK0# IRQ14 IRQ15 IRQ12 IRQ11 IRQ10 IOCS16# MEMCS16# LFRAM# PCIRST#
9
NOTE3: For K/B functions pow setting used
24.576M OSC 14.318M PWRDN# SERIRQ LDRQ# PCICLK
FOR AC97 CODEC
R2 4.7K NOTE8 : For 25.000 MHz clock setting used .
LAD[3..0] LAD[3..0] AVCC3 VCC3 VCC5 C3 0.1UF C1 0.1UF C6 10UF/16V
C2 0.1UF
NOTE2: If do not use the clock output function ,please connect to GND.(Pin 27,28&29)
inbond
Title W83626F FOR LPC TO ISA BRIDGE Size B Date: Document Number 626_1.SCH Tuesday, November 16, 1999
WINBOND ELECTRON
- 18 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
5VCC RP9 VCC5 RP1 RP4 SA[18..0] For 8M BIOS ROM decode 32 VCC5 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 2 3 4 5 6 7 8 9 10 1 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 IRQ11 2 3 4 5 6 7 8 9 10 1 VCC5 U2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 IRQ12 IRQ14 IRQ15 MEMCS16# IOCS16# IOCHK# OWS# SMEMW# SMEMR# 2 3 4 5 6 7 8 9 10 8.2K 1
8.2K VCC5 RP2 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 2 3 4 5 6 7 8 9 10 8.2K VCC5 RP3 SA1 SA0 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 2 3 4 5 6 7 8 9 10 8.2K VCC5 DRQ0 DRQ1 DRQ2 DRQ3 1 3 5 7 1 LAD0 LAD1 LAD2 LAD3 LDRQ# SERIRQ LFRAM# 2 3 4 5 6 7 8 1 LAD0 LAD1 LAD2 LAD3 LDRQ# SERIRQ LFRAM# 2 3 4 5 6 7 8
8.2K VCC3 RP11
1
1 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
VCC
SD[7..0] DRQ5 DRQ6 DRQ7 MASTER#
RP8 1 3 5 7 8.2K 2 4 6 8
8.2K NOTE6: For disconnected signals used VCC3 RP10 MEMW# MEMR# ROMCS# 31 24 22 WE# OE# CE# GND 16
W29C040P-90 (PLCC)
1 VCC5 R8 8.2K RP5 2 4 6 8 8.2K 4.7K NOTE4: R7 for ROMCS# power-on setting used. The circuit is for flashable ROM For BIOS read-only used can connect OE# and CE# together to ROMCS# and without MEMR# and MEMW#.
No used signals
R4 IOCHRDY MEMW# IOR# R5 MEMR# IOW# R10 R7 R6
1K 8.2K 8.2K 8.2K R9 8.2K PWRDN# 4.7K NOTE7 : Reserved for wake_up function. PD[0..7] RP6 2 3 4 5 6 7 8 9 10 1 VCC5 STB# AFD# INIT# SLIN# ERR# ACK# BUSY PE SLCT 2 3 4 5 6 7 8 9 10 RP7 1 VCC5 VCC3
Flash ROM Decoder
ISA I/F PULL HIGH OR PULL DOWN RESISTORS
4.7K 4.7K
PRT PULL-HI RESISTORS
VCC5
VCC3
VCC5
VCC3
CB5 0.1uF
CB1 0.1uF
CB2 0.1uF
CB3 0.1uF
CB4 0.1uF
C7 10uF/16V
C8 10uF/16V
C9 10uF/16V
C10 10uF/16V
inbond
WINBOND ELECTRONICS CORP. Title W83626F FOR LPC TO ISA BRIDGE Size Document Number Custom 626_2.SCH Date: Tuesday, August 24, 1999 Sheet 2 of 4 Rev 0.3
- 19 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
PD[0..7] VCC5 J4 FIRRX IRRX IRTX SA10 IOHCS# CS# SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 1 2 3 4 5 HEADER 5 C19 PD3 U3 180PF C20 180PF C22 180PF PD0 PD1 PD2 C17 180PF 180PF C18 C16
SA[0..10]
SA[0..10]
51
52
53
54
55
57
58
59
60
61
75
2 CS#/A11
IR CONNECTOR
180PF PD4 C21 PD5 180PF
SD[0..7]
SD[0..7] SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 66 67 68 69 70 71 72 73 6 62 5 63 64 97 44 37 99 23 39 41 100 98 4 18 U4 1 NC OUTPUT 24MHz OSC 5 7 CLKIN
D0 D1 D2 D3 D4 D5 D6 D7
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
VCC5 34 33 32 31 30 38 35 36 HEFRAS
VCC5 C12
PD6 PD7 C23 180PF
CTSA# DSRA# DCDA# RIA# SINA SOUTA/PENFDC DTRA#/HEFRAS RTSA#/PPNPCVS
CTSA DSRA DCDA RIA SINA SOUTA DTRA RTSA
R13 4.7K
C14 C15 0.1UF/6.3V
0.1UF/6.3V
RSTDRV AEN IOCHRDY IOR# IOW# TC IRQ3 IRQ4 IRQ6 IRQ7 DRQ1 DACK1# DRQ2 DACK2# DRQ3 DACK3#
MR AEN IOCHRDY IOR# IOW# T/C IRQC/IRQ3 IRQD/IRQ4 IRQF/IRQ6 IRQE/IRQ7 DRQA/DRQ1 DACKA#/DACK1# DRQB/DRQ2 DACKB#/DACK2# DRQC/DRQ3 DACKC#/DACK3#
0.1UF/16V C13 U5 0.1UF/16V 12 14 15 16 7 6 20 21 8 5 26 22 19 10 C1+ C1C2+ C2T1IN T2IN T3IN T4IN R1OUT R2OUT R3OUT R4OUT R5OUT GND MAX232E V+ VT1OUT T2OUT T3OUT T4OUT R1IN R2IN R3IN R4IN R5IN VCC (SOP) C11 0.1UF/16V 13 17 J2 2 3 1 28 9 4 27 16 18 11 NSOUTA NRTSA NDTRA NDCDA NSINA NDSRA NCTSA NRIA VCC5 STB# AFD# PD0 ERR# PD1 INIT# PD2 SLIN# PD3 PD4 PD5 PD6 PD7 ACK# J3 NDCDA NSOUTA GND NRTSA NRIA SLIN# INIT# AFD# STB# 1 3 5 7 9 2 4 6 8 10 NSINA NDTRA NDSRA NCTSA BUSY PE SLCT 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DB25 C28 STB# STB# 180PF C29 180PF C31 180PF C24 180PF C26 180PF AFD# C30 INIT# SLIN# ERR# ACK# BUSY PE INIT# 180PF SLIN# ERR# ACK# BUSY 180PF PE C27 PD[0..7] PD[0..7] SLCT SLCT 180PF C32 180PF C25
CTSB#/A12 DSRB#/A13 DCDB#/A14 RIB#/A15 SINB
47 48 49 50 42 R12
SOUTA RTSA DTRA DCDA SINA DSRA CTSA RIA
SOUTB/PIRQMDS DTRB# RTSB#/PGOIQSEL
43 46 45
PIRQMDS 4.7K
NOTE5 : DRQ0 & DACK0# Set by CR2B & CR2C
8
SMI# ERR# ACK# BUSY PE SLCT
IRQ5 IRQ10 DRQ0 DACK0# IRRX IRTX FIRRX J1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 IRRXH
96 92 1 91 94 95 93 3
IRQA/GIO1 IRQB/GIO0 IRQG/PCICLK IRQH/SERIRQ IRRX2 IRTX2 IRQIN IRRXH/SCI#
29 26 24 27 28 RP13
ERR# ACK# BUSY PE SLCT
SLIN# INIT# AFD# STB#
22 21 20 19
1 3 5 7
2 4 6 8
CN2X5B COMA (UARTA)
33 RP12 RWC# INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# 87 81 79 84 83 80 89 82 86 85 78 77 74 88 76 RWC# INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# PD0 PD1 PD2 PD3 9 10 11 12 1 3 5 7 33 13 14 16 17 1 3 5 7 RP14 2 4 6 8 PD4 PD5 PD6 PD7 2 4 6 8 PD0 PD1 PD2 PD3
COM
AFD#
PD4 PD5 PD6 PD7 VCC VCC
33 VSS VSS VSS VSS
15
56
25
40
65
VCC5
D1 1N5817/19 R11 0
90
HEAD17X2 FDC
W83877F/AF/TF/ATF
CB6 0.1UF VCC5 +12V -12V
PRT
CB10 0.1UF
CB11 0.1UF
CB7 0.1UF
CB8 0.1UF
CB9 0.1UF
TC1 10UF/16V
TC2 10UF/16V
TC3 10UF/16V
TC4 10UF/16V
+
+
+
+
+
TC5 10UF/16V
inbond
TitleWINBOND ELECTRONICS CORP. W83626F FOR LPC TO ISA BRIDGE Size Document Number Custom 626_3.SCH Date: Tuesday, August 24, 1999 Sheet 3 of 4 Rev 0.3
- 20 -
Publication Release Date: Feb 2000 Revision 0.50
LPC TO ISA BRIDGE SET W83626F/W83626D
PRELIMINARY
- 21 -
Publication Release Date: Feb 2000 Revision 0.50

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